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20- bit, 1.8 msps, precision sar, differential adc data sheet AD4020 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2017 analog devices, inc. all rights reserved. technical support www.analog.com features throughput: 1.8 msps maximum inl: 3 .1 ppm maximum guaranteed 20 - bit no missing codes low power 9.0 mw at 1.8 msps (vdd o nly) 8 3 w at 10 ksps, 1 5 mw at 1.8 msps (total) snr : 100.5 db typical at 1 k hz, 99 db typical at 100 k hz thd: ? 123 db typical at 1 k hz, ? 100 db typical at 1 00 k hz ease of use features reduce system power and complexity input o ver v oltage c lamp circuit reduced n on linear i nput charge kick back high - z m ode long acquisition phase input s pan c ompression fast conversion time allows l ow sp i clock rates spi - programmable modes, r ead/ w rite capability , s tatus w ord d ifferential analog input range: v ref 0 v to v ref with v ref from 2 .4 v to 5. 1 v single 1.8 v s upply operation with 1.71 v to 5.5 v logic interface sar architecture : n o latency/pipeline delay valid first accurate conversion guaranteed o peration : ?40c to + 125c serial interface : spi/qspi/microwire/dsp compatible ability to daisy - chain multiple adcs and busy indicator 10- lead package s : 3 mm 3 mm lfcsp , 3 mm 4.90 mm msop applications automatic t est e quipment machine a utomation medical e quipment battery - powered equipment precision d ata acquisition systems general description the AD4020 is a low noise, low power, high speed , 20- bit , 1.8 msps precision successive approximation register (sar) analog - to - digital converter (adc) . it incor porates ease of use features that lower the signal chain power, reduc e signal chain complexity , and enable higher channel density. the high - z mode , coupled with a long acquisition phase , eliminates the need for a dedicated high power, high speed adc driver, thus broadening the range of low power precision amplifiers that can drive this adc directly , while stil l achieving optimum performance. the input span compression feature enables the adc driver amplifier and the adc to operate off common supply rails without the need for a negative supply while preserving the full adc code range. the low serial peripheral interface ( spi ) clock rate requiremen t reduces the digital input/output power consumption, broadens processor options , and simplifies the task of sending data across digital isolation. operating from a 1.8 v supply, the AD4020 has a v ref fully differenti al input range with v ref ranging from 2. 4 v to 5.1 v. the AD4020 cons umes only 1 5 mw at 1.8 msps with a minimum sck rate of 71 mhz in turbo mode and achieves 3 . 1 ppm integral nonlinearity ( inl ) , guaranteed no missing codes at 20 bits with 100 .5 db typical signal - to - noise ratio ( snr ) . the reference voltage is applied externally and can be set independent ly of the supply voltage. the spi - compatible versatile serial interface features seven different modes including the ability, using the sdi input, to daisy - chain several adcs on a single 3 - wire bus , and provides an optional busy indicator. the AD4020 is compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the AD4020 is av ailable in a 10 - lead msop or a 10 - lead lfcsp with operation specified from ? 40c to +125c . the device is pin compatible with the 18- bit, 2 msps ad4003 . functional block dia gram gnd in+ in? sdi sck sdo cnv AD4020 20-bit sar adc serial interface vio ref vdd v ref 0 v ref 0 v ref /2 v ref /2 high-z mode clamp span compression turbo mode status bits 2.5v to 5v 1.8v 10f 1.8v to 5v 3-wire or 4-wire spi interface (daisy chain, cs) 15369-001 figure 1 .
AD4020* product page quick links last content update: 08/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? evaluation board for the ad4000 series 16-/18-/20-bit precision sar adcs documentation data sheet ? AD4020: 20-bit, 1.8 msps, precision sar, differential adc data sheet user guides ? ug-1042: evaluation board for the ad4000 series 16-/18- bit precision sar adcs software and systems requirements ? ad4000 series fpga device driver tools and simulations ? ad4000 series ibis models reference designs ? cn0385 design resources ? AD4020 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD4020 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
AD4020 data sheet rev. a | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 6 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 14 theory of operation ...................................................................... 15 circuit information .................................................................... 15 converte r operation .................................................................. 15 transfer functions ...................................................................... 16 applications information .............................................................. 17 typical application diagrams .................................................. 17 analog inputs ............................................................................. 19 driver amplifier choic e ........................................................... 20 ease of drive features ............................................................... 22 voltage reference input ............................................................ 23 powe r supply ............................................................................... 24 digital interface .......................................................................... 24 register read/write functionality ........................................... 25 status word ................................................................................. 27 cs mode, 3 - wire tur b o mo d e ................................................. 28 cs mode, 3 - wire without the busy indicator ....................... 29 cs mode , 3 - wire with the busy indicator .............................. 30 cs mode, 4 - wire tur b o mo d e ................................................. 31 cs mode, 4 - wire without the busy indicator ........................... 32 cs mode, 4 - wire with the busy indicator .............................. 33 daisy - chain mode ..................................................................... 34 layout guidelines ....................................................................... 35 evaluating the AD4020 performance ...................................... 35 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 7/2017 rev. 0 to rev. a change to integral nonlinearity error (inl) parameter , table 1 ................................................................................................ 3 7/ 2017 revis ion 0: initial version
data sheet AD4020 rev. a | page 3 of 36 specifications vdd = 1.71 v to 1.89 v , v io = 1. 71 v to 5 .5 v , v ref = 5 v , all specifications t min to t max , h igh - z m ode disabled, span compression disabled , a nd turbo mode enabled ( f s = 1.8 msps ) , unless otherwise note d. table 1. parameter test conditions/comments min typ max unit resolution 20 bits analog input voltage range v in+ ? v in? ? v ref + v ref v span c ompression enabled ? v ref 0. 8 + v ref 0. 8 v operating input voltage v in+ , v in? to gnd ?0.1 + v ref + 0.1 v span c ompression enabled 0.1 v ref 0.9 v ref v common - mode input range v ref /2 ? 0.125 v ref /2 v ref /2 + 0 .125 v common - mode rejection ratio ( cmrr ) f in = 500 khz 68 db analog input current acquisition phase , t a = 25c 0.3 na high - z mode enabled , converting dc input at 1.8 msps 1 a throughput complete cycle 555 ns conversion time 300 320 350 ns acquisition phase 1 325 ns throughput rate 2 (f s ) 0 1.8 msps transient response 3 325 ns dc accuracy no missing codes 20 bits integral nonl inearity error (inl) ?3 .1 1 +3 .1 ppm t = 0c to 70c ? 2 1 + 2 ppm differential nonlinearity error (dnl) ?0.5 0. 3 +0.5 lsb transition noise 3.3 lsb zero error ? 35 +3 5 lsb zero error drift 4 ? 0.3 + 0.3 ppm/c gain error ? 88 12 + 88 lsb gain error drift 4 ? 1.2 + 1.2 ppm/c power supply sensitivity vdd = 1.8 v 5% 6 lsb 1/f noise 5 bandwidth = 0.1 hz to 10 hz 6 v p -p ac accuracy dynamic range 101 db total rms n oise 31.5 v rms f in = 1 khz, ?0.5 dbfs, v ref = 5 v signal -to - noise ratio (snr) 99 100.5 db spurious - free dynamic range (sfdr) 122 db total harmonic distortion (thd) ?123 db signal -to - noise - and - distortion ratio (sinad) 98.5 100 db oversampled dynamic range oversampling ratio (osr) = 256, v ref = 5 v 122 db f in = 1 khz, ?0.5 dbfs, v ref = 2.5 v snr 93.3 94.7 db sfdr 122 db thd ?119 db sinad 93 94.5 db
AD4020 data sheet rev. a | page 4 of 36 parameter test conditions/comments min typ max unit f in = 100 khz, ?0.5 dbfs, v ref = 5 v snr 99 db thd ?100 db sinad 96.5 db f in = 400 khz, ?0.5 dbfs, v ref = 5 v snr 92.5 db thd ?94 db sinad 90 db ?3 db input bandwidth 10 mhz aperture delay 1 ns aperture jitter 1 ps rms reference voltage range (v ref ) 2.4 5.1 v current 1.8 msps , v ref = 5 v 1.1 ma overvoltage clamp i in+ /i in? v ref = 5 v 50 ma v ref = 2.5 v 50 ma v in+ /v in? at maximum i in+ /i in? v ref = 5 v 5.4 v v ref = 2.5 v 3.1 v v in+ /v in? clamp on/off threshold v ref = 5 v 5.25 5.4 v v ref = 2.5 v 2.68 2.8 v deactivation time 360 ns ref current at maximum i in+ /i in? v in+ /v in? > v ref 100 a digital inputs logic levels input voltage low ( v il ) vio > 2.7 v ?0.3 +0.3 vio v vio 2.7 v ?0.3 +0.2 vio v input voltage high (v ih ) vio > 2.7 v 0.7 vio vio + 0.3 v vio 2.7 v 0.8 vio vio + 0.3 v input current low (i il ) ?1 +1 a input current high (i ih ) ?1 +1 a input pin capacitance 6 pf digital outputs data format serial , 20 bits, twos complement pipeline delay conversion results available immediately after completed conversion output voltage low ( v ol ) i sink = 500 a 0.4 v output voltage high ( v oh ) i source = ?500 a vio ? 0.3 v power supplies vdd 1.71 1.8 1.89 v vio 1.71 5.5 v standby current vdd = 1.8 v, vio = 1.8 v, t a = 25c 1.6 a power dissipation vdd = 1.8 v, vio = 1.8 v, v ref = 5 v 10 ksps, high - z mode disabled 83 w 1 msps, high - z mode disabled 8.3 mw 1.8 msps , high - z mode disabled 15 19 mw 1 msps, high - z mode enabled 10.8 mw 1.8 msps , high - z mode enabled 19 25 mw vdd only 1.8 msps , high - z mode disabled 9.0 mw ref only 1.8 msps , high - z mode disabled 5.0 mw
data sheet AD4020 rev. a | page 5 of 36 parameter test conditions/comments min typ max unit vio only 1.8 msps , high - z mode disabled 1.0 mw energy per conversion 8.3 nj/sample temperature range specified performance t min to t max ?40 +125 c 1 the acquisition phase is the t ime available for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 1.8 msps . 2 a throughput rate of 1.8 msps can only be achieved with turbo mode enabled and a minimum sck rate of 71 mhz. refer to table 4 for the maximum achievable throughput for different modes of operation. 3 transient response is the time required for the adc to acquire a full - scale inp ut step to 2 lsb accurac y. 4 the minimum and maximum values are guaranteed by characterization , but not production tested. 5 see the 1/f noise plot in figure 18.
AD4020 data sheet rev. a | page 6 of 36 timing specification s vdd = 1.71 v to 1.89 v , vio = 1.71 v to 5.5 v , v ref = 5 v , all specifications t min to t max , high - z mode disabled, span compression disabled , and turbo mode enabled ( f s = 1.8 msps ) , unless otherwise noted . see figure 2 for the timing voltage levels. table 2. digital interface timing parameter symbol min typ max unit conversion time cnv rising edge to data available t conv 300 320 350 ns acquisition phase 1 t acq 325 ns time between conversions t cyc 555 ns cnv pulse width ( cs mode) 2 t cnvh 10 ns sck period t sck cs mode 3 vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns daisy - chain mode 4 vio > 2.7 v 20 ns vio > 1.7 v 25 ns sck low time t sckl 3 ns sck high time t sckh 3 ns sck falling edge to data remains valid delay t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv or sdi low to sdo d17 msb valid delay ( cs mode) t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns cnv rising edge to first sck rising edge delay t quiet1 200 ns last sck falling edge to cnv rising edge delay 5 t quiet2 60 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 2 ns sdi valid hold time from cnv rising edge cs mode t hsdicnv 2 ns daisy - chain mode t hsckcnv 12 ns sdi valid setup time from sck rising edge (daisy - chain mode) t ssdisck 2 ns sdi valid hold time from sck rising edge (daisy - chain mode) t hsdisck 2 ns 1 the acquisition phase is the t ime available for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 1.8 msps . 2 for turbo mode, t cnvh must match the t quiet1 minimum. 3 a throughput rate of 1.8 msps can only be achieved with turbo mode enabled a nd a minimum sck rate of 71 mhz. 4 a 50% duty cycle is assumed for sck. 5 see figure 22 for sinad vs. t quiet2 . x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 2.7v, x = 80, and y = 20; for vio > 2.7v, x = 70, and y = 30. 2 minimum v ih and maximum v il used. see the digital inputs specifications in table 1. 15369-002 figure 2 . voltage levels for timing
data sheet AD4020 rev. a | page 7 of 36 table 3 . register read/write timing parameter symbol min typ max unit read/write operation cnv pulse width 1 t cnvh 10 ns sck period t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck time low t sckl 3 ns high t sckh 3 ns read operation cnv low to sdo d1 7 msb valid delay t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns sck falling edge to data remains valid t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv r ising e dge to sdo high impedance t dis 20 ns write operation sdi valid setup time from sck rising edge t ssdisck 2 ns sdi valid hold time from sck rising edge t hsdisck 2 ns cnv rising edge to sck edge hold time t hcnvsck 0 ns cnv falling edge to sck active edge setup time t scnvsck 6 ns 1 for turbo mode, t cnvh must match the t quiet1 minimum. table 4 . achievable throughput for different modes of operation parameter test conditions/comments min typ max unit throughput , cs mode 3- wire and 4 - wire turbo mode f sck = 100 mhz, vio 2.7 v 1.80 msps f sck = 80 mhz, vio < 2.7 v 1.80 msps 3- wire and 4 - wire turbo mode and six status bits f sck = 100 mhz, vio 2.7 v 1.80 msps f sck = 80 mhz, vio < 2.7 v 1.67 msps 3- wire and 4 - wire mode f sck = 100 mhz, vio 2.7 v 1.61 msps f sck = 80 mhz, vio < 2.7 v 1.49 msps 3- wire and 4 - wire mode and six status bits f sck = 100 mhz, vio 2.7 v 1.47 msps f sck = 80 mhz, vio < 2.7 v 1.34 msps
AD4020 data sheet rev. a | page 8 of 36 absolute maximum rat ings table 5. parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0. 4 v, or 50 ma supply voltage ref , vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to + 2.1 v vdd to vio ?6 v to +2.4 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature soldering 260c reflow as per jedec j - std -020 esd ratings human body model 4 kv machine model 200 v field induced charged device model 1.25 kv 1 see the analog inputs section for an explanation of in+ and in?. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may aff ect product reliability. note that the clamp cannot sustain the overvoltage condition for an indefinite time. thermal resistance t hermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to p cb thermal design is required. table 6 . thermal resistance package type ja jc unit rm - 10 1 147 38 c/w cp -10-9 1 114 33 c/w 1 test condition 1: thermal impedance simulated values are based upon use of 2s2p jedec pcb. see the ordering guide . esd caution
data sheet AD4020 rev. a | page 9 of 36 pin configurations a nd function descript ions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 AD4020 t o p view (not to scale) 15369-003 figure 3 . 10 - lead msop pin configuration 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9 sdi 8 sck 7 sdo 6 cnv AD4020 t o p view (not to scale) notes 1. connect the exposed pad to gnd. this connection is not required to meet the specified performance. 15369-004 figure 4 . 10 - lead lfcsp pin configuration table 7 . pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the v ref range is 2 .4 v to 5 .1 v. this pin is referred to the gnd pin and must be decoupled closely to the gnd pin with a 10 f x7r ceramic capacitor. 2 vdd p 1.8 v power supply. the range of vdd is 1.71 v to 1.89 v. bypass vdd to gnd with a 0.1 f ceramic capacitor . 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the device : daisy - chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in daisy - chain mode, the data is read wh en cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows . chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 20 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. with cnv low, the device can be programmed by clocking in a 16 - bit word on sdi on the rising edge of sck. 10 vio p input/output interface digital power. nominally , this pin is at the same supply as the host interface (1.8 v , 2.5 v, 3 v, or 5 v). bypass v io to gnd with a 0.1 f ceramic capacitor. n/a 2 epad p exposed pad (lfcsp only). connect the exposed pad to gnd. this connection is not required to meet the specified performance. 1 ai is analog input, p is power , di is digital input, and do is digital output. 2 n/a means not applicable.
AD4020 data sheet rev. a | page 10 of 36 typical performance characteristics vdd = 1.8 v , vio = 3.3 v , v ref = 5 v , t = 25c, high - z mode disabled, span compression disabled , and turbo mode enabled ( f s = 1.8 msps ), unless otherwise noted. 2.0 1.5 1.0 in l (ppm) 0 ?0.5 0.5 ?1.0 ?1.5 ?2.0 0 131072 262144 393216 524288 code 655360 786432 917504 1048576 +125c +25c ?40c 15369-005 figure 5 . inl vs. code for various temperature s , v ref = 5 v 2.0 1.5 1.0 in l (ppm) 0 ?0.5 0.5 ?1.0 ?1.5 ?2.0 0 131072 262144 393216 524288 code 655360 786432 917504 1048576 +125c +25c ?40c 15369-005 figure 6 . inl vs. code for various temperatures , v ref = 2.5 v 3 2 in l (ppm) 0 1 ?1 ?2 ?3 0 131072 262144 393216 524288 code 655360 786432 917504 1048576 15369-007 high-z enabled span compression enabled f igure 7 . inl vs. code for high - z and span compression modes enabled, v ref = 5 v 1.0 0.8 0.6 dnl (ppm) 0 ?0.2 ?0.4 0.2 0.4 ?0.6 ?0.8 ?1.0 0 131072 262144 393216 524288 code 655360 786432 917504 1048576 15369-008 +125c +25c ?40c figure 8 . dnl vs. code for various temperatures , v ref = 5 v 1.0 0.8 0.6 dnl (ppm) 0 ?0.2 ?0.4 0.2 0.4 ?0.6 ?0.8 ?1.0 0 131072 262144 393216 524288 code 655360 786432 917504 1048576 15369-009 +125c +25c ?40c figure 9 . dnl vs. code for various temperatures , v ref = 2.5 v 1.0 0.8 0.6 dn l (ppm) 0 ?0.2 ?0.4 0.2 0.4 ?0.6 ?0.8 ?1.0 0 131072 262144 393216 524288 code 655360 786432 917504 1048576 15369-008 high-z enabled span compression enabled figure 10 . dnl vs. code for high - z and span compression modes enabled, v ref = 5v
data sheet AD4020 rev. a | page 11 of 36 0 50000 100000 150000 200000 250000 524210 524220 524230 524240 524250 524260 524270 code count adc code 2.5v code center 5v code center 15369-0 1 1 figure 11 . histogram of a dc input at code center, v ref = 2.5 v and v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 900k frequency (hz) v ref = 5v snr = 100.33db thd = ?123.99db sinad = 100.31db 15369-012 figure 12 . 1 khz, 0.5 dbfs input tone fft, wide view , v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 900k frequency (hz) v ref = 5v snr = 98.37db thd = ?98.52db sinad = 95.58db 15369-013 figure 13 . 100 khz, 0.5 dbfs input tone fft, wide view 0 50000 100000 150000 200000 250000 524205 524215 524225 524235 524245 524255 524265 code count adc code 2.5v code transition 5v code transition 15369-014 f igure 14 . histogram of a dc input at code transition, v ref = 2.5 v and v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 900k frequency (hz) v ref = 2.5v snr = 95.01db thd = ?118.60db sinad = 94.99db 15369-015 figure 15 . 1 khz, 0.5 dbfs input tone fft, wide view, v ref = 2.5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 900k frequency (hz) v ref = 5v snr = 91.22db thd = ?91.97db sinad = 89.15db 15369-016 figure 16 . 400 khz, 0.5 dbfs input tone fft, wide view
AD4020 data sheet rev. a | page 12 of 36 102 97 99 100 101 98 95 96 94 16.6 15.4 15.6 15.8 16.0 16.2 16.4 snr, sinad (db) enob (bits) 2.4 4.8 4.5 3.9 4.2 3.6 3.3 3.0 2.7 5.1 reference voltage (v) enob sinad snr 15369-017 figure 17 . snr, sinad, and enob vs. reference voltage 60 58 55 56 59 57 54 adc output reading (v) 0 9 8 5 6 7 4 3 2 1 10 time (seconds) 15369-018 figure 18 . 1/f noise for 0.1 hz to 10 hz bandwidth, 50 k sps , 2500 samples averaged per reading 95 100 105 110 115 120 125 130 135 140 0 2 4 8 16 32 64 128 256 512 1024 snr (db) decimation rate dr f in = 1khz f in = 10khz 15369-019 figure 19 . snr vs. decimation rate for various input frequencie s ?114 ?124 ?120 ?118 ?116 ?122 ?128 ?126 ?130 133 126 127 128 130 129 131 132 thd (db) sfdr (db) 2.4 4.8 4.5 3.9 4.2 3.6 3.3 3.0 2.7 5.1 reference voltage (v) sfdr thd 15369-020 figure 20 . thd and sfdr vs. reference voltage 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 reference current (ma) reference voltage (v) 15369-021 figure 21 . reference current vs. reference voltage t 93 94 95 96 97 98 99 100 101 0 10 20 30 40 50 60 70 80 sinad (db) t quiet2 (ns) vio = 5.5v vio = 3.6v vio = 1.89v 15369-022 figure 22 . sinad vs. t quiet2
data sheet AD4020 rev. a | page 13 of 36 100.8 100.0 100.4 100.6 100.2 99.6 99.8 99.4 16.42 16.22 16.24 16.26 16.28 16.30 16.32 16.34 16.36 16.38 16.40 snr, sinad (db) enob (bits) temperature (c) enob sinad snr 15369-023 ?40 100 80 60 40 20 0 ?20 120 figure 23 . snr, sinad, and enob vs. temperature, f in = 1 khz 0 1 2 3 4 5 6 7 8 9 10 o p e a r t i ng c u rr e n t ( m a ) t e m p e r a t u r e ( c) ?40 100 80 60 40 20 0 ?20 120 v dd h i g h - z d i s a b l e d v i o h i g h - z d i s a b l e d v r e f h i g h - z d i s a b l e d v dd h i g h - z e n a b l e d v i o h i g h - z e n a b l e d v r e f h i g h - z e n a b l e d 15369-024 figure 24 . operating current vs. temperature ?6 ?4 ?2 0 2 4 6 8 10 z e r o e rr o r an d ga i n e rr or ( l s b ) t e m p e r a t u r e ( c) ?40 100 80 60 40 20 0 ?20 120 15369-025 z e r o e r r or p f s g a in e r r o r n fs g ain e r r o r figure 25 . zero error and gain error vs. temperature (pfs is positive full scale and nfs is negative full scale ) ?114.0 ?114.5 ?116.5 ?115.5 ?115.0 ?116.0 ?117.0 ?117.5 118.0 117.9 117.4 117.7 117.8 117.6 117.2 117.3 117.5 117.1 117.0 thd (db) sfdr (db) ?40 100 80 60 40 20 0 ?20 120 temperature (c) thd sfdr 15369-026 figure 26 . thd and sfdr vs. temperature, f in = 1 khz 25.0 20.0 10.0 15.0 5.0 22.5 17.5 7.5 12.5 2.5 0 standby current ( a) ?40 100 80 60 40 20 0 ?20 120 temperature (c) 15369-027 figure 27 . standby current vs. temperature 23 21 13 17 19 15 9 11 7 5 t dsdo (ns) 0 100 80 60 40 200 180 160 140 20 220 120 load capacitance (pf) vio = 5v vio = 3.3v vio = 1.8v 15369-028 figure 28 . t dsdo vs. load capacitance
AD4020 data sheet rev. a | page 1 4 of 36 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negati ve full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 30). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first tra nsition (from 100 00 to 100 01) occurs at a level ? lsb above nominal negative full scale (?4.9999 95 v for the 5 v range). the last transition (from 011 10 to 011 11) occurs for an analog voltage 1? lsb below the nominal full scale (+4.9999 86 v fo r the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious - free dynamic range (sfdr) sfdr is the d ifference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows: enob = ( sinad db ? 1. 76)/6.02 enob is expressed in bits. noise free code resolution noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise free code resolution = log 2 (2 n / peak - to - peak noise ) noise free code resolution is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) effective resolution is expressed in bits. total harmonic distortion (thd) thd is the ratio o f the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. the value for dynam ic range is expressed in decibels. it is measured with a signal at ?60 dbfs so that it includes all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectr al components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spec tral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to acquire a full - scale input step to 1 lsb accuracy. common - mode rejection ratio (cmrr) cmrr is the ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave applied to the common - mode voltage of in+ and in? of frequency, f. cmrr (db) = 10log( p adc_in / p adc_out ) where: p adc_in is the common - mode power at the frequency, f, applied to the in+ and in? inputs. p adc_out is the power at the frequency, f, in the adc output. power supply rejection ratio (psrr) psrr is the ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave applied to the adc vd d supply of frequency, f. psrr (db) = 10 log( p vdd_in / p adc_out ) where: p vdd_in is the power at the frequency, f, at the vdd pin. p adc_out is the power at the frequency, f, in the adc output.
data sheet AD4020 rev. a | page 15 of 36 theory of operation comp control logic sw i t c h es c o n t r o l b u s y o u t pu t c o d e c n v c c 2c 262,144c 4c 524,288c lsb sw+ msb lsb sw? msb c c 2c 262,144c 4c 524,288c in+ ref gnd in? 15369-029 figure 29 . adc simplified schematic circuit information the AD4020 is a high speed , low power, single - supply, precise, 20- bit adc based on a sar architecture. the AD4020 is capable of converting 1 ,8 00,000 sam ples per second ( 1.8 msps ) and powers down between conversions. when operating at 10 ksps, for example, it typically consumes 8 3 w , making it ideal for battery - powered applications because its power scales linearly with throughput. the AD4020 has a valid first conversion after being powered down for long periods. the AD4020 provides the user with an on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiplexed applications. the AD4020 incorporate s a multitude of unique ease of use features that result in a lower system power and footprint . the AD4020 has an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. the analog input incorporates circuitry that reduces the nonline ar charge kick back seen from a t ypical switched capacitor sar input . th is reduction in kickback , combined with a longer acquisition phase , means reduced settling requirements on the driving amplifier . this combination allows the use of lower bandwidth and lower power amplifiers as drivers. it has the additional benefit of allowing a larger resistor value in the input rc filter and a corresponding smaller capacitor , which results in a smaller rc load for the amplifier , improving stability and power dissipati on. h igh - z m ode can be enabled via the spi interface by programmin g a register bit (see table 14) . when h igh - z m ode is enabled , the adc input has a low input charging current at low input signal frequencies as well as improved distortion over a wide frequenc y range up to 100 k hz . for fre quencies above 100 k hz and multiplexing , disable h igh - z mode. for single - supply applications , a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the adc. the fast conversion time of the AD4020 , along with turbo mode , allow s low clock rates to read back conversions even when runnin g at the full 1.8 msps throughput rate. note that a throughput rate of 1.8 msps can be achieved only with turbo mode enabled and a minimum sck rate of 7 1 mhz. the AD4020 can be interfaced to any 1.8 v to 5 v digital logic family. it is available in a 10 - lead msop or a tiny 10 - lead lfcsp that allows space savings and flexible configurations. the AD4020 is pin for pin compatible with some of the 14 - /16 - / 18- bit precision sar adcs listed in table 8 . table 8 . msop and lfcsp 14- /16 - /18- /20- bit precision sar adcs bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps 20 1 not applicable not applicable not applicable AD4020 2 18 1 ad7989 - 1 2 ad7691 2 ad7690 2 , ad7989 - 5 2 , ad4011 2 ad4003 2 , ad4007 2 , ad7982 2 , ad7984 2 16 1 ad7684 ad7687 ad7688 2 , ad7693 2 ad4001 2 , ad4005 2 , ad7915 2 16 3 ad7680 , ad7683 , ad7988 - 1 2 ad7685 , 2 ad7694 2 ad7686 2 , ad7988 - 5 2 ad4000 2 , ad4004 2 , ad7980 2 , ad7983 2 14 3 ad7940 ad7942 2 ad7946 2 not applicable 1 true differential. 2 pin for pin compatible. 3 pseudo differential. converter operation the AD4020 is a sar - based adc using a charge redistribution sampling digital - to - analog converter ( dac ) . figure 29 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 20 bin ary weighted capacitors, which are connected to the comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via the sw+ and sw? switches . all independent switches connect the other terminal of each capacitor to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs.
AD4020 data sheet rev. a | page 16 of 36 when the acquisition phase is complete and the cnv input goes high, a conv ersion phase i nitiate s . when the conversion phase begins, sw+ and sw? open s first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. t he differential voltage between the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and v ref , the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 , , v ref / 1,048,576 ). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and a busy signal indicator. be cause the AD4020 has an on - board conversion clock, the serial clock, sck, is not required for the conversion process. transfer functions the ideal transfe r characteristic s for the AD4020 are shown in figure 30 and table 9 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 15369-030 figure 30 . adc ideal transfer function (fsr is full - scale range) table 9 . output codes and ideal input voltages description analog input, v ref = 5 v v ref = 5 v with span compression enabled digital output code (hex) fsr ? 1 lsb +4.9999 9046 v +3.99999 237 v 0x 7ffff 1 midscale + 1 lsb +9.54 v +7.63 v 0x00001 midscale 0 v 0 v 0x00000 midscale ? 1 lsb ?9.54 v ?7.63 v 0x fffff ?fsr + 1 lsb ? 4.99999046 v ? 3.99999237 v 0x 80001 ?fsr ?5 v ?4 v 0x 80000 2 1 this output code is also the code for an overranged analog input (v in+ ? v in? above v ref ). 2 this output code is also the code for an underranged analog input (v in+ ? v in ? below ? v ref ).
data sheet AD4020 rev. a | page 17 of 36 applications informa tion typical application diagram s figure 31 shows an example of the typical application diagram for the AD4020 when multiple supplies are available. this configuration is used for optimal performance because the amplifier supplies can be selected to allow the maximum signal range. figure 32 shows a typ ical application diagram when using a single - supply system. this setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. figure 33 shows a typical application diagram when using a fully differential amplifier. c r v+ ref vdd vio gnd in+ in? sdi sck sdo cnv AD4020 3-wire/4-wire interface 1.8v 1.8v to 5v v+ +6.5v digital host (microprocessor/ fpga) v? ?0.5v host supply 0.1f 0.1f 5v c r v? v+ v? amp amp v ref 0v v ref 0v v ref /2 v ref /2 ref ldo amp v ref /2 10f 10k 10k 15369-031 figure 31 . typical application diagram with multiple supplies
AD4020 data sheet rev. a | page 18 of 36 c r ref vdd vio gnd in+ in? sdi sck sdo cnv AD4020 2 1.8v 1.8v to 5v v+ = +5v digital host (microprocessor/ fpga) host supply 0.1f 0.1f 100nf 100nf 4.096v c r amp amp v ref 0 v ref 0 v ref /2 v ref /2 ref 1 ldo amp v ref /2 10f 2 10k 10k 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x7r). 3 see the driver amplifier choice section. 4 see the analog inputs section. 3-wire/4-wire interface 3, 4 15369-032 figure 32 . typical application diagram with a single supply 10f ref vdd vio gnd in+ in? sdi sck sdo cnv AD4020 3-wire/4-wire interface 1.8v 1.8v to 5v digital host (microprocessor/ fpga) 4.096v 0.1f v ocm r3 1k? +in v+ ?in ?out +out r4 1k? 10k 10k r2 1k? r r differential amplifier r1 1k? 0.1f v ref /2 host supply v? c c ref v+ = +5v ldo amp v ref 0 v ref /2 v ref 0 v ref /2 0.1f v ref /2 15369-033 figure 33 . typical application diagram with a fully differential amplifier
data sheet AD4020 rev. a | page 19 of 36 analog inputs figure 34 shows an equivalent circuit of the analog input structure , including the overvoltage clamp of the AD4020 . c ext r ext v in ref d1 in+/in? gnd clamp 0v to 15v r in c in d2 c pin 15369-034 figure 34 . equivalent analog input circuit input over v oltage clamp circuit most adc analog inputs, in+ and in?, have no overvoltage protection circuitry apart from esd protection diodes. during an overvoltage event, an esd protection diode from an analog input (in+ or in?) pin to ref forward biases and shorts the input pin to ref, potentially overloading the reference or causing d amage to the device. the AD4020 internal overvoltage clamp circuit with a larger external resistor (r ext = 200 ?) elim inates the need for external protection diodes and protects the adc inputs against dc overvoltages. in applications where the amplifier rails are greater than v ref and less than ground , it is possible for the output to exceed the input voltage range of the device. in this case, the AD4020 internal voltage clamp circuit ensures that the voltag e on the input pin does not exceed v ref + 0.4 v and prevents damage to the device by clamping the input voltage in a safe operating range and avoid ing disturbance of th e reference ; this feature is particu - larly importa nt for systems that share the reference among multiple adcs. if the analog input exceeds the reference voltage by 0.4 v, t h e internal clamp circuit turns on and the current flows through the clamp into ground, preventin g the input from rising further and potentially causing damage to the device. the clamp turns o n before d1 (see figur e 34) and can sink up to 50 ma of current. when active, the clamp sets the overvoltage ( ov ) clamp flag bit in the register that can be read back (see table 14 ), which is a sticky bit that must be read to be cleared. the status of the clamp can also be checked in the status bits using an overvoltage ( ov ) clamp flag (see table 15 ). the clamp circuit does not dissipate static power in the off state. note that the clamp cannot sustain the overvoltage condition for an indefinite amou nt of time. the external rc filter is usually present at the adc input to band limit the input signal. during an overvoltage event, excessive voltage is dropped across r ext , and r ext becomes part of a protection circuit. the r ext value can vary from 200 ? to 20 k? for 15 v protection. the c ext value can be as low as 100 pf for correct operation of the clamp. see table 1 for inp ut overvoltage clamp specifications. differential input c onsiderations the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differentia l inputs, signals common to both inputs are rejected. figure 35 shows the common - mode rejection capability of the AD4020 over frequency. it is important to note that the differential i nput signals must be truly anti phase in nature , 180 out of phase , which is re quired to keep the common - mode voltage of the input signal within the specified range around v ref /2 , as shown in table 1 . 72 71 70 69 68 67 66 cmrr (db) 100 1k 10k 100k 1m frequency (hz) 15369-035 figure 35 . common - mode rejection ratio (cmrr) vs . frequency, v io = 3.3 v, v ref = 5 v, t a = 25c switched capacitor input during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 4 00 ? and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 40 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are open , the input impedance is limited to c pin . r in and c in make a single - pole, low - pass filter that reduces undesirable aliasing effects and limits noise.
AD4020 data sheet rev. a | page 20 of 36 rc f ilter v alues the value of the rc filter (represented by r and c in figu re 31 to figure 33 and figure 36) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full 1.8 msps throughput. lower input signal bandwidth means that the rc cutoff can be lower , thereby reducing noise into the converter. for optimum performance at various throughput s , use the recommended rc values (200 ?, 180 pf) and the ada4807 - 1 . the rc values i n table 10 are chosen for ease of drive considera - tions and greater adc input protection. the combination of a large r value (200 ? ) and small c value result s in a reduced dynamic load for the amplifier to drive. the smaller value of c means less stabilit y and phase margin concerns with the amplifier. the large value of r limit s the current into the adc input when the amplifier outpu t exceeds the adc input range. driver amplifier cho ice although the AD4020 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept low enough to preserve the snr and transition noise perform ance of the AD4020 . the noise from the driver is filtered by the single - pole, low - pass filter of the analog input circuit of the AD4020 made by r in and c in , or by the external filter, if one is used. because the typical noise of the AD4020 is 3 1.5 v rms, the snr degradatio n due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 31.5 31.5 log 20 n db 3 loss ne f snr ere f ? 3 db is the input bandwidth, in megahertz, of the AD4020 ( 10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent in put noise voltage of the op amp in nv/hz. ? for ac applications, the driver must have a thd performance commensurate with the AD4020 . ? for multichannel multiplexed applications, the driver amplifier and the analog input circuit of the AD4020 must settle for a full - scale step onto the capacitor array at a 20- bit level (0.000 01 %, 1 ppm). in the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. this may differ significan tly from the settling time at a 20- bit level and must be verified prior to driver selection. table 10 . rc filter and amplifier selection for various input bandwidths input signal bandwidth (khz) r (?) c (pf) recommended amplifier recommended fully differential amplifier <10 see the high - z mode section see the high - z mode section see the hig h - z mode section ada4940 -1 <200 200 180 ada4807 -1 ada4940 -1 >200 200 120 ada4897 -1 ada4932 -1 multiplexed 200 120 ada4897 -1 ada4932 -1
data sheet AD4020 rev. a | page 21 of 36 ref vdd vio gnd in+ in? sdi sck sdo cnv AD4020 1.8v to 5v +in ?in r4 1k? differential amplifier r1 1k? v? amp v ref v ref /2 0 1.8v 10f r 3 1k? v+ ?out +out r2 1k? r r 0.1f v ref /2 host supply c c ref v+ = +5v ldo 10k 10k v ocm 4.096v 0.1f 0.1f 3-wire/4-wire interface digital host (microprocessor/ fpga) v ref /2 15369-036 figure 36 . typical application diagram for single - ended to differential conversion with a fully differential amplifier single to differential driver for applications using a single - ended analog signal, either bipolar or unipolar, the ada4940 - 1 s ingle - ended to differential driver allows a differential input to the device. the schematic is shown in figure 36. high frequency input signals the AD4020 ac performance over a wide input frequency range is shown in figure 37 and figure 38 . unlike other traditional sar adcs, the AD4020 maintains exceptional ac performance for input frequencies up to the nyquist frequency with minimal performance degradation. 102 96 90 100 92 94 98 88 17.0 15.5 16.5 14.5 15.0 16.0 14.0 snr, sinad (db) enob (bits) 1k 100k 10k 900k input frequency (hz) enob sinad snr 15369-037 figure 37 . snr, sinad , and enob vs. input frequency ?90 ?105 ?95 ?115 ?110 ?100 ?120 120 105 115 95 100 110 90 thd (db) sfdr (db) 1k 100k 10k 900k input frequency (hz) thd sfdr 15369-038 figure 38 . thd and sfdr vs. input frequency
AD4020 data sheet rev. a | page 22 of 36 multiplexed applications the AD4020 significantly reduce s system complexity and cost for multiplexed applications that require superior performance in terms of noise, power, and throughput. figure 39 shows a simplified block diagram of a multiplexed data acquisition system including a multiplexer, an adc driver, and the precision sar adc. 15369-139 sar adc adc driver multiplexer sensors r r r c c c c figure 39 . multiplexed data acquisition signal chain using the AD4020 switching multiplexer cha nnels typically results in large voltage steps at the adc inputs. to ensure an accurate conversion result, the step must be given adequate time to settle before the adc samples its inputs (on the rising edge of cnv). the settling time error is dependent on the drive circuitry (multiplexer and adc driver), rc filter values , and the time when the multiplexer cha nnels are switched. switch t he multiplexer channels immediately after t quiet1 has elapsed from the start of t he conversion to maximize settling time while preventing corruption of the conversion result. to avoid conversion corruption, do not s witch the cha nnels during the t quiet1 time. if the analog inputs are multiplexed during th e quiet conversion time (t quiet1 ), the current conversion may be corrupted. ease of drive featur es input span compression in single - supply applications, it is desirable to use the full range of the adc; however, the amplifier can have some headroom and footroom requirements, which can be a problem, even if it is a rail - to - rail input and output amplifier. the use of span compression increases the headroom and footroom available to t he amplifier by reducing the input range by 10% from the top and bottom of the range while still ac cessing all available adc codes ( see figure 40 ) . the snr decreases by approximately 1.9 db (20 l og(8/10)) for the reduced input range when span compression is enabled. span compression is disabled by default but can be enabled by writin g to the relevant register bit ( see the digital interface section ) . adc v ref = 4.096v digital output all 2 n codes +fsr ?fsr 90% of v ref = 3.69v 10% of v ref = 0.41v analog input 5v in+ 15369-039 figure 40 . span compression high - z m ode the AD4020 incorporates high - z mode , which reduces the non linear charge kickback when the capacitor dac switches back to the input at the start of acquisition. figure 41 shows the input current of the AD4020 with h igh - z mode enabled and disabled. the low input current makes the adc easier to drive than the traditional sar adcs available in the market , even with high - z mode disabled. the input current reduces furth er to submicroampere range when high - z mode is enabled. the high - z mode is disabled by default, but it can be enabled by writing to the register (see tabl e 14 ). disable high- z mode for input frequencies above 100 khz or multiplexing. 15 6 ?12 ?6 12 0 3 ?9 9 ?3 ?15 input current (a) ?5 3 1 ?1 ?3 5 2 0 ?2 ?4 4 input differential voltage (v) 25c high-z enabled 25c high-z disabled 15369-040 figure 41 . input current vs . input differential voltage , vio = 3.3 v, v ref = 5 v s ystem designers looking to achieve the optimum data sheet performance from hig h resolution precision sar adcs are ofte n forced to use a dedicated high power, high speed amplifier to drive the traditional switched capacitor sar adc inputs for their precision applications , which is one of the common pain points encountered in designing a precision data acquisition signal chain. the benefits of high - z mode are low input current for slow (<10 k hz) or dc type signals and improved distortion (thd) performance over a frequency up to 100 khz. high - z mode allows a choice of lower power and bandwidth precision amplifiers with a lower rc filter cutoff to drive the adc , removing the need for dedicated high speed adc drivers, which sav es system power, size , and cost in precision, low bandwidth applications. high - z mod e allows the amplifier and rc filter in front of the adc to be chosen based on the signal bandwidth of interest and not based on the settling requirements of the switched capacitor sar adc inputs.
data sheet AD4020 rev. a | page 23 of 36 additionally , the AD4020 can be driven with a much h igher source impedance than traditional sars , which means the resistor in the rc filter can have a value 10 times larger than previous sar designs and , with h igh - z mode enabled , can tolerate an even larger impedance. f igure 42 shows the thd performance for various source impedances with high - z mode disabled and enabled. ?85 ?90 ?100 ?110 ?95 ?105 ?115 ?120 ?125 thd (db) 1 10 20 input frequency (khz) 1k ? high-z disabled 1k ? high-z enabled 510 ? high-z disabled 510 ? high-z enabled 150 ? high-z disabled 150 ? high-z enabled 15369-041 figure 42 . thd vs. input frequency for various source impedance s , v r ef = 5 v figure 43 and figure 44 show the AD4020 snr and thd performance using the ada4077 - 1 (i quiescent = 400 a per amplifier) and ada4610 - 1 ( i quiescent = 1.5 ma per amplifier) precision amplifiers when driving the AD4020 at the full throughput of 1.8 msps for h igh - z mode enabled and disabled with various rc filter values. these amplifiers achieve + 96 db t o + 99 db typical snr and better than ? 110 db thd with high - z enabled. thd is approximately 10 db better with high - z mode enabled , even for large r values. snr maintains close to 99 db , even with a very low rc bandwidth cutoff. 100 97 91 85 94 88 82 76 79 73 70 260khz 1.3k ? 470pf 498khz 680 ? 470pf 2.27mhz 390 ? 180pf 1.3mhz 680 ? 180pf 4.42mhz 200 ? 180pf snr (db) rc filter bandwidth (hz) resistor (), capacitor (pf) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled 15369-042 figure 43 . snr vs. rc filter bandwidth for v arious precision adc drivers, v ref = 5 v, f in = 1 khz (turbo mode o n , high - z e nabled/ d isabled) ?80 ?84 ?92 ?100 ?88 ?96 ?104 ?112 ?108 ?116 ?120 thd (db) 260khz 1.3k ? 470pf 498khz 680 ? 470pf 2.27mhz 390 ? 180pf 1.3mhz 680 ? 180pf 4.42mhz 200 ? 180pf rc filter bandwidth (hz) resistor (), capacitor (pf) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled 15369-043 figure 44 . thd vs. rc filter bandwidth for v arious precision adc drivers, v ref = 5 v, f in = 1 khz (turbo mode o n , high - z e nabled/ d isabled) when high - z mode is enabled, the adc consumes approximately 2 .0 mw per m sps extra power; however, this is still significantly lower than using dedicated adc drivers like the ada4807 - 1 . for any system, the front end usually limits the overall ac/dc performance of the signal chain. it is evident from the data sheet of the selected precision ampl ifiers shown in figure 43 and figure 44 that their own noise and distortion performance dominates the snr and thd specification at a certain input frequency. long acquisition phase the AD4020 also features a very fast conversion time of 320 ns , which r esults in a long acquisit ion phase . the ac quisition is further extended by a key feature of the AD4020 ; th e adc r eturn s to the acquisition phase typically 100 ns before the end of the conversion . this feature provides an even longer time for the adc to acquire the new input voltage. a longer acquisition phase reduces the settling requirement on the driving amplifier , and a lower power/bandwidth amplifier can be chosen. the longer acquisition phase means that a lower rc filter (represented by r and c in figure 31 to figure 33 and figure 36) cutoff can be used , which means a noisier amplifier can also be tolerated. a larger value of r can be used in the rc filter with a corresponding smaller value of c , reducing amplifier stabil ity concerns without impacting distortion performance significantly. a larger value of r also results in reduced dynamic power dissipation in the amplifier. see table 10 for details on setting the rc filter bandwidth and choosing a suitable amplifier. voltage reference in put a 10 f (x7 r, 0 8 0 5 size) ceramic chip capacitor is appropriate for the optimum performance of the reference input . for higher performance and lower drift , use a reference such as the adr4550 . u se a low power reference such as the adr3450 at the expense of a sl ight decrease in the noise performance . it is recommended to use a reference buffer , such as the ada480 7 - 1 , between the refere nce and the adc reference input. it is important
AD4020 data sheet rev. a | page 24 of 36 to consider the optimum size of capacitance necessary to keep the reference buffer stable as well as to meet the minimum adc requirement stated previously in this section . power supply the AD4020 uses two power supply pins: a core supply (vdd) and a digita l input/output interface supply (vio). vio allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio and vdd can be tied together for 1.8 v operation . the adp7118 low noise , cmos , low drop out (ldo) linear regulator is recommended to power the vdd and vio pins . the AD4020 is independent of power supply sequencing between vio and vdd. additionally, the AD4020 is insensitive to power supply variations over a wide frequency range, as shown in figure 45. 80 75 70 65 60 55 50 psrr (db) 100 1k 10k 100k 1m frequency (hz) 15369-044 figure 45 . psrr vs . frequency , vio = 3.3 v , v ref = 5 v the AD4020 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this feature makes the device ideal for low sampling rates (even of a few hertz) and battery - powered applications. figure 46 shows the AD4020 total power dissipation and individual power dissipation for each rail. 0.01 0.10 1 10 100 1k 10k 100k 10 100 1k 10k 100k 1m 1.8m power dissi pa tion (w) throughput (sps) v dd v io v ref total power 15369-146 figure 46 . power dissipation vs. throughput, vio = 1.8 v , v ref = 5 v digital interface although the AD4020 has a reduced number of pins, it offers flexibility in its serial interface modes. the AD4020 can also be programmed via 16 - bit spi writes to the configuration registers. when in cs mode, the AD4020 is compatible with spi, qspi ? , digital hosts, a nd dsps. in this mode, the AD4020 can use either a 3 - wire or 4 - wire i nterface. a 3 - wire interface using the cnv, sck, and sdo signals minimizes wiring connections , which is useful, for instance, in isolated applications. a 4 - wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this interface is useful in low jitter sampling or simultaneous sampling applications. t he AD4020 provides a daisy - chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the device operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and daisy - chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, daisy - chain mode is always selected. in either 3 - wire or 4 - wire mode , the AD4020 offers the option of forcing a start bit in front of the data bits. th is start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled i n cs mode if cnv or sdi is low when the adc conversion ends. the sdo state upon power - up is high - z for a few milliseconds and it change s to either low or h igh - z depending on the states of cnv and sdi , as shown in in table 11. table 11 . state of sdo upon power -up cnv sdi sdo 0 0 l ow 0 1 low 1 0 low 1 1 high -z the AD4020 has a turbo mode capability in both 3 - wire and 4 - wire mode. turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enabled. tur b o mo d e allows a slower spi clock rate , making interfacing simpler. a throughput rate of 1.8 msps can be achieved only with turbo mode enabled and a minimum sck rate of 7 1 mhz.
data sheet AD4020 rev. a | page 25 of 36 status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration register. there are six status bits in total as described in table 12. the AD4020 is configured by 16 - bit spi writes to the desired configuration register. t he 16 - bit word c an be written via the sdi line while cnv is held low . the 16 - bit word consists of an 8 - bit header and 8 - bit register data. for isolated systems, the adum141d is recommended, which has a max imum clock rate of 75 mhz and allows the AD4020 to run at 1.8 msps . register read/write functionality the AD4020 register bits are programmable and their default status es are shown in table 12 . the register map is shown in table 14. the overvoltage clamp flag is a read only stic ky bit , and it is cleared only if the register is read and the overvoltage condition is no longer present. it gives an indication of overvoltage condition when it i s set to 0. table 12 . register bits register bits default status overvoltage ( ov ) clamp flag 1 bit (default 1: inactive) turbo mode 1 bit (default 0: disabled) high - z mode 1 bit (default 0: disabled) span compression 1 bit (default 0: disabled) enable six status bits 1 bit (default 0: disabled) all access to the register map must start with a write to the 8 - b it command register in the spi interface block. the AD4020 ignores all 1 s until the first 0 is clocked in; the value loaded into th e command register is always a 0 followed by seven command b its. this command determines whether that operation is a write or a read. the AD4020 command register is shown in table 13. table 13 . command register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wen r/ w 0 1 0 1 0 0 all register read/writes must occur while cnv is low. data on sdi is clocked in on the rising edge of sck. data on sdo is clocked out on the falling edge of sck. at the end of the data transfer , sdo is put in a high impedance state on the rising edge of cnv if daisy - chain mode is not enable d . if daisy - chain mode is enabled , sdo goes low on the rising edge of cnv. register reads a re not allowed in daisy - chain mode. register write requires three signal lines: sck, cnv, and sdi. during register write, to read the current conversion results on s do, the cnv pin must be brought low after the conversion is completed ; otherwise, the conversion results may be incorrect on sdo ; however, the register write occur s regardless . the lsb of each configuration register is reserved because a user reading 16 - bi t conversion data may be limited to a 16 - bit spi frame. the state of sdi on the last bit in the sdi frame may be the state that then persists as cnv rises. because the state of sdi when cnv rises is part of how the user sets the interface mode, the user in this scenario may need to set the final sdi state on that basis. the timing diagram s in figure 47 through figure 49 show how data is read and written when the AD4020 is configured in register read, write , and daisy - chain mode. table 14. register map addr [1:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0x0 reserved reserved reserved enable six status bits span compression high - z mode turbo mode overv oltage ( ov ) c lamp f lag (read only sticky bit ) 0x e1 t cyc t sck t dis t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh t en cnv sck 1 2 3 4 5 6 7 0 1 1 0 1 0 1 0 0 b0 b1 b2 b3 b4 b5 b6 wen r/w 0 1 0 1 addr[1:0] 8 9 10 11 12 13 14 15 16 sdi sdo t hsdo t dsdo b7 x d19 d18 d17 d16 d15 d14 d13 d12 15369-046 figure 47 . register read timing diagram
AD4020 data sheet rev. a | page 26 of 36 1 conversion result on d[17:0] t cyc t sck t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh 1 t en cnv sck 1 2 3 4 5 6 7 0 0 1 0 1 0 1 0 0 wen r/w 0 1 0 1 addr[1:0] 8 9 10 11 12 13 14 15 16 17 18 19 20 sdi sdo t hsdo t dsdo t dis t hcnvsck 1 the user must wait t conv time when reading back the conversion result, while performing a register write at the same time. 15369-047 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 b0 b1 b2 b3 b4 b5 b6 b7 figure 48 . register write timing diagram sdi a sdo a /sdi b sdo b 0 0 command (0x14) 0 0 command (0x14) 0 0 command (0x14) t cyc t sck t sck l t sckh t scnvsck cnv sck 1 24 t dis t cnvh data (0xab) data (0xab) 15369-048 figure 49 . register w rite timing diagram , d aisy - c hain m ode
data sheet AD4020 rev. a | page 27 of 36 status word the 6 - bit status word can be appended to the end of a conversion result , and the default conditions of these bits ar e defined in table 15 . the status bits must be enabled in the register setting. when the overvoltage clamp flag is a 0 , it indicat es an overvoltage condition . the overvoltage clamp flag status bit updates on a per conversion basis. the sdo line goes to high - z after the sixth status bit is clocked out (except in daisy - chain mode). the user is not required to clock out all status bits to start the next conversion. the serial interface timing for cs m ode, 3 - w ire without busy indicator , including status bits , is shown in figure 50. table 15. status b its ( d efault condition s ) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 overvoltage ( ov ) clamp flag span compression high - z mode turbo mode reserved reserved sdo d19 d18 d17 d1 d0 sck 1 2 3 18 19 20 t sck t sck l t sckh t hsdo t dsdo cnv conversion acquisition t cyc acquisition sdi = 1 t cnvh t acq t en 25 26 t quiet2 status bits b[5:0] b1 t dis b0 24 t conv 15369-049 figure 50 . cs mode, 3 - wire without busy indicator serial interface timing diagram i ncluding status bits (sdi high)
AD4020 data sheet rev. a | page 28 of 36 cs mode, 3- wire turbo mode this mode is typically used when a single AD4020 is connected to an spi - compatible digital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result, providing a lower sck rate. the AD4020 can achieve a throughput rate of 1.8 msps only when turbo mode is enabled and using a minimum sck rate of 7 1 mhz. the connection diagram is shown in figure 51, and the corresponding timing diagram is shown in figure 52 . this mode replaces the 3 - wire with busy indicator mode by programming the turbo mode bit , bit 1 (see table 14 ). when sdi is forced high, a rising edge on cnv initiates a conversion. the previous conversion data is available to read after the cnv rising edge. t he user must wait t quiet1 time after cnv is brought high before bringing cnv low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the AD4020 enters the acquisition phase and powers down. when cn v goes low, the msb is output to sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck fallin g edge allows a faster reading rate, provided it has an acceptable hold time. after the 20 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. AD4020 sdi sdo cnv sck convert data in clk digital host vio 15369-050 figure 51 . cs mode, 3 - wire turbo mode connection diagram (sdi high) sdo d19 d18 d17 d1 d0 t dis sck 1 2 3 18 19 20 t sck t sck l t sckh hsdo t dsdo cnv acquisition t cyc acquisition conversion sdi = 1 t acq t en t quiet1 t quiet2 t conv 15369-051 figure 52 . cs mode, 3 - wire turbo mode serial interface timing diagram (sdi high)
data sheet AD4020 rev. a | page 29 of 36 cs mode, 3- wire without the busy indicator this mode is typically used when a single AD4020 is connected to an spi - compatible digital host. the connection diagram is shown in figure 53 , and the corresponding timing diagram is shown in figure 54. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. after a conversion is initiated, it continues until completion irrespectiv e of the state of cnv. this feature can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then h eld high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the c onversion is complete, the AD4020 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. afte r the 20 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. there must not be any digital activity on sck during the con version. AD4020 sdi sdo cnv sck convert data in clk digital host vio 15369-052 figure 53 . cs mode, 3 - wire without the busy indicator connection diagram (sdi high) sdo d19 d18 d17 d1 d0 t dis sck 1 2 3 18 19 20 t sck t sck l t sckh hsdo t dsdo cnv conversion acquisition t cyc acquisition sdi = 1 t cnvh t acq t en t quiet2 t conv 15369-053 figure 54 . cs mode, 3 - wire without the busy indicator serial interface timing diagram (sdi high)
AD4020 data sheet rev. a | page 30 of 36 cs mode, 3- wire with the busy indicator this mode is typically used when a single AD4020 is connected to an spi - compatible digital host with an interrupt input ( irq ) . the connection diagram is shown in figure 55 , and the corresponding timing diagram is shown in figure 56. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the co mpletion of the c onversion irrespective of the state of cnv. prior to the minimum c onversion time, cnv can select other spi device s, such as analog multiplexers; however, cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull - up resistor of 1 k? on the sdo line, this transition can be use d as an interrupt signal to initiate the data reading controlle d by the digital host. the AD4020 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sc k edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 21 st sck falling edge or when cnv goes high (whichever occurs first) , sdo returns to high impedance. if multiple AD4020 device s are selected at the same time, the sdo output pin handles this contention without damage or induced latch - up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. there must not be any digital activity on the sck during the conversion . sdi sdo cnv sck convert d at a in clk digital host vio irq vio 1k? AD4020 15369-054 figure 55 . cs mode, 3 - wire with the busy indicator connection diagram (sdi high) sdo d19 d18 d1 d0 t dis sck 1 2 3 19 20 21 t sck t sck l t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t quiet2 15369-055 figure 56 . cs mode, 3 - wire with the busy indicator serial interface timing diagram (sdi high)
data sheet AD4020 rev. a | page 31 of 36 cs mode, 4- wire turbo mode this mode is typically used when a single AD4020 is connected to an spi - compatible digital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result , giving a lower sck rate. the AD4020 c an achieve a throughput rat e of 1.8 msps only when turbo mode is enabled and using a minimum sck rate of 7 1 mhz. the connection diagram is shown in figure 57 , and the correspond ing timing diagram is shown in figure 58. this mode replaces the 4 - wire with busy indicator mode by programming the turbo mode bi t , bit 1 (see table 14). the previous conversion data is available to read after th e cnv rising edge. t he user must wait t quiet1 time after cnv is brought high befo re bringing sdi low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the AD4020 enters the acquisition phase and powers down. the adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. a pull - up resistor of 1 k? on the sdo line is recommended. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 20 th sck falling edge or when sdi goes high (whichever occurs first) , sdo returns to high impedance. AD4020 sdi sdo cnv sck convert data in clk digi t a l host irq vio 1k? cs1 15369-056 figure 57 . cs mode, 4 - wire turbo mode connection diagram acquisition sdo sck acquisition sdi cnv t ssdicnv t hsdicnv t cyc t sck t sck l t en t hsdo 1 2 3 18 19 20 t dsdo t dis t sckh d19 d18 d17 d1 d0 t quiet1 t quiet2 t acq conversion t conv 15369-057 figure 58 . cs mode, 4 - wire turb o m ode timing diagram
AD4020 data sheet rev. a | page 32 of 36 cs mode, 4 - wire without the busy indicator this mode is typically used when multiple AD4020 device s are connected to an spi - compatible digital host. a connection diagram example using two AD4020 device s is shown in figure 59 , and the corresponding timing is shown in figure 60. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the con version phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select o ther spi devices, such as analog multiplexers ; however, sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the c onversion is complete, the AD4020 enters the acquisition phase and powers down. each adc result can be read by bringi ng its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck fa lling edge allows a faster reading rate, provided it has an acceptable hold time. after the 20 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance and another AD4020 can be read. AD4020 sdi sdo cnv sck AD4020 sdi sdo cnv sck device b device a convert data in clk digital host cs1 cs2 15369-058 figure 59 . cs mode, 4 - wire without the busy indicator connection diagram sdo d19 d18 d17 d1 d0 t dis sck 1 2 3 38 39 40 t hsdo t dsdo t en conversion acquisition t conv cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 18 19 t sck t sck l t sckh d0 d19 d18 21 22 20 sdi(cs2) t quiet2 15369-059 figure 60 . cs mode, 4 - wire without the busy indicator serial interface timing diagram
data sheet AD4020 rev. a | page 33 of 36 cs mode, 4- wire with the busy indicator this mode is typically used wh en a single AD4020 is connected to an spi - compatible digital host with an interrupt input , and when it is desired to keep cnv, which sample s the analog input, independent of the signal used to select the data reading. this independence is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown i n figure 61 , and the corresponding timing is shown in figure 62. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi device s, such as analog multiplexers; however, sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull - up resistor of 1 k ? on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by t he digital host. the AD4020 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital hos t using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 21 st sck falling edge or when sdi goes high (whichever occurs first) , sdo returns to high impedance. sdi sdo cnv sck cs1 convert dat a in clk digital host irq vio 1k? AD4020 15369-060 figure 61 . cs mode, 4 - wire with the busy indicator connection diagram sdo d0 d1 d18 d19 t dis sck 1 2 3 19 20 21 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv t quiet2 15369-061 figure 62 . cs mode, 4 - wire with the busy indicator serial interface timing diagram
AD4020 data sheet rev. a | page 34 of 36 daisy - chain mode use t his mode to daisy - chain multiple AD4020 device s on a 3 - wire or 4 - wire serial interface. this feature is useful for reducing c omponent count and wiring connections, for example, in isolated multiconverte r applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two AD4020 device s is shown in figure 63 , and the corresponding timing is shown in figure 64. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects daisy - chain mode, and disables the busy indicator. in this mode, cnv is held h igh during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo , and the AD4020 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are cl ocked out of sdo by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck rising edge s . each adc in the daisy - chain outputs its data msb first, and 20 n clocks are required to read back t he n adcs. the data is valid on both sck edges. the maximum conversion rate is reduced due to the total readback time. it is possible to write to each adc register in daisy - chain mode. the timing diagram is shown in f igure 49 . this mode requires 4 - wire operation because data is clocked in on the sdi line with cnv held low. the same command byte and register data can be shifted through the entire chain to program all adcs in the chain with the same register contents , which requires 8 (n + 1 ) clocks for n adcs. it is pos sible to write different register contents to each adc in the chain by writing to the furthest adc in the chain , first using 8 (n + 1) clocks , and then the second furthest adc with 8 n clocks , and so forth until reaching the nearest adc in the chain , w hich require s 16 clocks for the command and register data . it is not possible to read register contents in daisy - chain mode ; however , the six status bits can be enabled if the user wants to know the adc configuration . note that enabling the status bits req uires six extra clocks to clock out the adc result and the status bits per adc in the chain. tur b o mode cannot be used in daisy - chain mode. convert data in clk digital host device b device a AD4020 sdi sdo cnv sck AD4020 sdi sdo cnv sck 15369-062 figure 63 . daisy - c hain mode connection diagram 15369-063 d a 19 d a 18 d a 17 sck 1 2 3 3 8 3 9 4 0 t ssdisck t hsdisck conversion acquisition t conv t cyc t acq acquisition cnv d a 1 1 8 1 9 t sck t sck l t sckh d a 0 2 1 2 2 2 0 sdi a = 0 sdo b d b 19 d b 18 d b 17 d a 1 d b 1 d b 0 d a 19 d a 18 t hsdo t dsdo t quiet2 t hsckcnv d a 0 t dis t quiet2 t en sdo a = sdi b figure 64 . daisy - chain mode serial interface timing diagram
data sheet AD4020 rev. a | page 35 of 36 layout guidelines the pcb that houses the AD4020 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the AD4020, with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD4020 is used as a shield. fast switching signals, such as cnv or clocks, must not run near analog signal paths. avoid crossover of digital and analog signals. at least one ground plane must be used. it can be common or split between the digital and analog sections. in the latter case, join the planes underneath the AD4020 devices. the AD4020 voltage reference input (ref) has a dynamic input impedance. decouple the ref pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to (ideally right up against) the ref and gnd pins, and connect them with wide, low impedance traces. finally, decouple the vdd and vio power supplies of the AD4020 with ceramic capacitors, typically 100 nf, placed close to the AD4020 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 65 and figure 66. evaluating the AD4020 performance other recommended layouts for the AD4020 are outlined in the user guide of the evaluation board for the AD4020 ( eval- AD4020fmcz ). the evaluation board package includes a fully assembled and tested evaluation board, user guide, and software for controlling the board from a pc via the eval-sdp-ch1z . 15369-064 figure 65 . example layout of the AD4020 (top layer) 15369-065 figure 66 . example layout of the AD4020 (bottom layer)
AD4020 data sheet rev. a | page 36 of 36 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 67 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed p a d 3.10 3.00 sq 2.90 coplanarity 0.08 t op view side view bottom vie w 0.20 min pkg-004362 02-07-2017-c for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 indic a t or area options (see detail a) detail a (jedec 95) figure 68 . 10 - lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 integral nonlinearity (inl) temperature range ordering quantity package description package option branding AD4020 brmz 3.1 ppm ?40c to +125c tube, 50 10- lead msop rm -10 c8l AD4020 brmz - rl7 3. 1 ppm ?40c to +125c reel, 1000 10- lead msop rm -10 c8l AD4020 bcpz - rl7 3. 1 ppm ?40c to +125c reel, 1500 10- lead lfcsp cp -10-9 c8l eval - AD4020 fmcz AD4020 evaluation board compatible with eval - sdp - ch1z 1 z = rohs compliant part. ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d15369 - 0 - 7/17(a)

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